Table of Content and PDF files

		SESSION 1: Opening
		Opening
	1.1	Designing low-power circuits: an industrial point of view (Invited paper)
		Dr. C. Heer Infineon, , Germany
		SESSION 2: High Level Power Modeling and Tools
	2.1	"A Power Modeling and Estimation Framework for VLIW-based Embedded Systems"
		L. Benini, D. Bruni, M. Chinosi, C. Silvano, V. Zaccaria, R. Zafalon Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy
	2.2	"Automatic Generation of Complexity Functions for High-Level Power Analysis"
		E. Schmidt, A. Schulz, L. Kruse, W. Nebel R&D Division Embedded Systems, OFFIS Research Inst., Germany
	2.3	"An RTL Power Estimation Tool with On-Line Model Building Capabilities"
		A. Bogliolo, I. Colonescu, R. Corgnati, E. Macii, M. Poncino Dip. di Automatica e Informatica, Politecnico di Torino, Italy
	2.4	"A Technique to Automate STG Analysis and Refinement for CSC and Normalcy"
		A.B. Smirnov, N. Starodoubtsev, I.V. Klotchkov, M. Goncharov UPC LSI, Universitat Politecnica de Catalunya, Spain
		SESSION 3: Instruction Level Power and Software Optimization
	3.1	"High-Level Energy Estimation for Embedded DSP Software"
		J. Laurent, E. Senn, N. Julien, E.Martin LESTER Lab, South Britanny University, France
	3.2	"An Accurate and Fine Grain Instruction-Level Energy Model supporting Software Optimizations"
		S. Steinke, M. Knauer, L. Wehmeyer, P. Marwedel Department of Computer Science 12, University of Dortmund, Germany
	3.3	"Effect of Data Transfer and Storage Optimization on Design Quality Factors of Multimedia Algorithms Realized on Instruction Set Processors"
		K. Masselos, F. Catthoor, C. E. Goutis, H. DeMan VLSI Design Lab., Department of Electrical and Computer Engineering, University of Patras, Greece
	3.4	"Static Footprint Control in Code Compression for Low-Energy Embedded Systems"
		L. Benini, A. Macii, E. Macii Dip. di Automatica e Informatica, Politecnico di Torino, Italy
	3.5	"Evaluating the Effect of Data-Reuse Transformations on Processor Power Consumption"
		A. Chatzigeorgiou, S. Kougia, S. Nikolaidis Department of Physics, Aristotle University of Thessaloniki, Greece
		SESSION 4: Gate Level Models and Interconnect
	4.1	"Area and Timing Models for PTL Macrocells"
		L. Benini, L. Macchiarulo, E. Macii Dip. Di Automatica e Informatica, Politecnico di Torino, Italy
	4.2	"A simple power consumption model of CMOS buffers driving RC interconnect lines"
		J.L. Rosselló, J. Segura Physics Dept., Balearic Islands University, Spain
	4.3	"Library sensitivity characterization to interconnect crosstalk"
		F. Picot, P. Coll, A. Landrault, P. Maurine, D. Auvergne ATMEL, France
	4.4	"Current-Sensing for Global Interconnects, Secondary Design Issues: Analysis and Solutions"
		A. Maheshwari, W. Burleson Electrical and Computer Engineering, University of Massachusetts, USA
		SESSION 5: Transistor and Gate Level Modeling
	5.1	“Analysis and Modeling of Deep-Submicron Issues in High-Performance Design” (Invited paper)
		D. Blaauw and K. Gala Motorola
	5.2	"DDM characterization methodology and automation"
		J.Juan-Chico, M.J. Bellido, P. Ruiz-de-Clavijo, C.J.Jimenez, C.Baena, M.Valencia Instituto de Microelectronica de Sevilla, Centro Nacional de Microelectronica - CSIC, Spain
	5.3	"Deep Submicron Switching Current Modeling for CMOS Logic Output Transition Time Determination"
		P. Maurine, N. Azemard, D. Auvergne LIRMM, MIC, University of Montpellier, France
		SESSION 6: Transistor and Gate Level Optimization
	6.1	"Digital Library for Mixed-Signal Applications: Overview and CAD tools" (Invited paper)
		M. Kayal and M. Pastre Swiss Federal Institute of Technology, Switzerland
	6.2	"Power-Efficiency Driven Device Sizing of Pass-Transistor Digital Circuits in Low-Voltage CMOS"
		L. Chen, M. Margala ECE Department, University of Rochester, USA
	6.3	"Analysis of Series-connected MOSFETs for Gate Delay Optimization"
		J.Merino, S.A.Bota, J.Samitier SIC- Departament d'electronica, Universitat de Barcelona, Spain
		SESSION 7: Power Efficient Technologies and Memories
	7.1	"Low-Power Design of Delay-Constrained Circuits Using Dual-VT Process Technology"
		P. Larsson-Edefors, H. Eriksson, D. Eckerbert, A. Alvandpour Dept. of Physics, Linköping University, Sweden
	7.2	"High Voltage Generation for Low Power Large VDD Range Non Volatile Memories"
		C. Papaix, J.-M. Daga ATMEL Rousset, France
	7.3	"High Speed, Low Power Design Rules for SRAM Precharge and Self-timing under Technology Variations"
		Th. Nirschl, B. Wicht, D. Schmitt-Landsiedel CPD DAT LIB S, Infineon Technologies AG, Germany
	7.4	"Low-Power SRAM and ROM Memories"
		J.-M. Masgonty, S. Cserveny, C. Piguet CSEM, Switzerland
		SESSION 8: Silicon On Insulator Techniques
	8.1	"Low-Power SOI Design" (Invited paper)
		M. Belleville and O. Faynot LETI, France
	8.2	"Branch-Based Logic for High Performance Carry-Select Adders in 0.25 µm Bulk and Silicon-On-Insulator CMOS technologies"
		A. Neve, D. Flandre Laboratoire de Microélectronique, Université Catholique de Louvain, Belgium
	8.3	"Power Supply Bus Sizing Considering Self-Heating in Bulk-to-SOI Migrated Designs"
		M. Casu, M. Graziano, G. Masera, G. Piccinini, M. Zamboni Electronics department, Politecnico di Torino, Italy
		SESSION 9: Adiabatic Design and Library Cells
	9.1	"Variations of the Power Dissipation in Adiabatic Logic Gates"
		E. Amirante, A. Bargagli-Stoffi, J. Fischer, G. Iannaccone, D. Schmitt-Landsiedel Institute for Technical Electronics, Technical University Munich, Germany
	9.2	"Control gates as building blocks for reversible computers"
		A. De Vos, B. Desoete, F. Janiak, and A. Nogawski Elektronica en Informatiesystemen, Universiteit Gent, Belgium
	9.3	"Reduction of Switching Noise in Digital CMOS Circuits by Pin Swapping of Library Cells"
		P. Parra, A.J. Acosta, M. Valencia Instituto de Microelectronica de Sevilla, IMSE-CNM/University of Seville, Spain
	9.4	"Low-Power Low-Voltage Standard Cell Libraries with a Limited Number of Cells"
		J.-M. Masgonty, S. Cserveny, C. Arm, P.-D. Pfister, C. Piguet CSEM, Switzerland
		SESSION 10: Low Power Issues in Processors and Arithmetic
	10.1	"A Comparative Power Analysis of an Asynchronous Processor"
		A. Efthymiou, J. D. Garside, S. Temple Department of Computer Science, University of Manchester, Great-Britain
	10.2	"Address Bus Power Exploration in Programmable Processors for Realization of Multimedia Applications"
		K. Tatas, M. Dasigenis, A. Argyriou, N. Kroupis, D. Soudris, and A. Thanailakis Dept. of Electrical & Computer Eng., Democritus University of Thrace, Greece
	10.3	"The Effect of Fault Secureness in Low Power Multiplier Designs"
		K.S. Papadomanolakis, A.P. Kakaroudas, V. Kokkinos, N. Sklavos, C.E. Goutis VLSI laboratory, department of Electrical Engineering, University of Patras, Greece
	10.4	"A New Low Power and High Speed Bidirectional Shift Register Architecture"
		N. Sklavos, P. Kitsos, N. Zervas and O. Koufopavlou VLSI Design Laboratory, University of Patras, Greece